<?xml version="1.0" encoding="utf-8"?><!DOCTYPE Zthes SYSTEM "http://zthes.z3950.org/schema/zthes-1.0.dtd">  <Zthes><term><termId>3305</termId><termName>Verilog (Lenguaje de descripción de material informático)</termName><termType>PT</termType><termLanguage>es-ES</termLanguage><termVocabulary>MATERIAS BUA</termVocabulary>	<termStatus>active</termStatus>	<termApproval>approved</termApproval>	<termSortkey>Verilog (Lenguaje de descripción de material informático)</termSortkey><termNote label="History"><![CDATA[ Admitida mayo 2003 ]]></termNote><termNote label="Source"><![CDATA[ Fuente: CSIC, LC ]]></termNote><termCreatedDate>Verilog (Lenguaje de descripción de material informático)</termCreatedDate><relation><relationType>BT</relationType><termId>26</termId><termName>1. ENCABEZAMIENTOS DE MATERIA</termName><termType>TT</termType></relation></term>  </Zthes>